`timescale 1ns / 1ps

module PC(
	input 		  clk,
	input 		  rst,
	input  [63:0] npc,
	input 		  stall,
	input		  if_stall,
  	input         switch_mode,
	input 		  predict_jump_exe,
	input		  jump,
	input  [63:0] alu_res,
  	input  [63:0] EXE_pc,
	input  [63:0] pc_csr,

	output reg [63:0] IF_pc,
	output     [63:0] IF_pc_4
);
reg [63:0] jump_pc;
reg lock;
always@(posedge clk)begin
    if(~lock & jump) begin 
		lock <= 1;
		jump_pc <= npc;
	end
    else if (lock && ~if_stall) begin
		lock <= 0;
	end
end



assign IF_pc_4 = IF_pc + 4;
always@(posedge clk)
begin
	if(rst) begin
		IF_pc <= 64'b0;
		// IF_vaild <= 1'b1;
	end
	else if(switch_mode) begin
		IF_pc <= pc_csr;
	end
	else if(predict_jump_exe && ~jump) begin
		IF_pc <= EXE_pc+4;
	end
	else if(lock && ~if_stall) begin
		IF_pc <= jump_pc;
	end
	else if(~stall) begin
		IF_pc <= npc;
	end
end

endmodule